Technical Seminar

Dr. Robert Ehlert, Intel Corporation

"Semiconductor process technology development at Intel Corp: Five years in Silicon Forest"

12:00pm, RLM 11.204

Abstract: Portland Technology Development (PTD), part of Intel’s Technology and Manufacturing Group (TMG), is the organization within Intel that is responsible for developing advanced silicon process technologies for microprocessor products. PTD is responsible for deciding what process features go into any new logic generation, then putting the technology elements together to make a working process flow, and finally running the process in pilot mode before transferring to high volume manufacturing fabs. Also located at the same Hillsboro site is Intel’s Components Research (CR) group. CR is responsible for exploring novel technology options several years before they might be used in manufacturing. Some of CR’s ideas are adopted by the PTD organization as they decide the features to be used in a new generation of process technology. To ensure that there is an effective handoff of new technology options from CR to PTD, members of each group work together in a temporary organization for a given technology generation called Pathfinding. This whole cycle of Research-Pathfinding-Development-Manufacturing is referred to as Intel’s Silicon R&D pipeline and has been a successful model for introducing new generations of process technology on regular two year intervals since the mid-1990’s. Dr. Ehlert will give an overview of Intel’s Hillsboro facilities and the research, development and manufacturing being done there.

Bio: Robert Ehlert, was born and grew up in Berlin, Germany where he received his Diplom in Physics from The Technical University of Berlin in 2005. He joined the non-linear spectroscopy group of Prof. Mike Downer in the fall of the same year and received his Ph.D in Physics from UT Austin in 2011, where his work focused on the nonlinear optical response of reconstructed silicon surfaces. After joining Intel’s Portland Technology Development (PTD) group he has focused on the development of novel epitaxial deposition techniques for strained silicon process technology. He has worked on Intel’s novel Tri-gate 22nm, 14nm and 10nm processes. Most recently he has been responsible for the nMOS S/D process development for the 10nm process node.